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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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622Mb/s Fiber Optic Post Amplifier
The LVSX1125 is an integrated low voltage limiting amplifier for high frequency fiber optic applications. The device interfaces directly to the trans-impedance amplifier of a typical optical to electrical conversion portion of a fiber optic link. With data rate capabilities in the 622Mb/s range, the high gain limiting amplification of the LVSX1125 is ideal for high speed fiber optic applications like SONET/SDM, ATM, FDDI, Fibre Channel or Serial Hippi. The device is functionally and pin compatible to the Philips SA5225 with a significantly higher bandwidth and lower voltage. The CAZP and CAZN inputs to the limiting amplifier provide an auto-zero function to effectively cancel any input offset voltage present in the amplifier. The LVSX1125 incorporates a programmable level detect function to identify when the input signal has been lost. This information can be fed back to the Disable input of the device to maintain stability under loss of signal conditions. Using the Vset pin the sensitivity of the level detect can be adjusted. The CLD input is used to filter the level detect input so that random noise spikes are filtered out. The MC10LVSX1125 is compatible with MECL10H logic levels.
MC10LVSX1125
FIBER OPTIC POST AMPLIFIER
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05
* * * * * *
Wideband Operation: 20kHz to 550MHz Programmable Input Signal Level Detection Operation with single +3.3V - 5V or standard ECL supply Standard 16-lead SOIC Package Fully Differential Design to Minimize Noise Affects 10KH Compatible BLOCK DIAGRAM
CAZP CAZN
Din Limiting Amplifier Din ECL Buffer
Dout Dout Vset 16 Vref VCCE Dout 15 14 13 Dout GNDE LOS 12 11 10 LOS 9
Pinout: 16-Lead Plastic Package (Top View)
Disable Vref Reference LOS LOS Disable
1 Level Detect ECL Buffer
2
3
4 Din
5 Din
CAZN CAZP GNDA
6 7 8 VCCA CLD Disable
Vset
CLD
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 08/1999
(c) Motorola, Inc. 1999
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REV 0
MC10LVSX1125
FUNCTION TABLE
Pin CAZN CAZP GNDA Din, Din VCCA CLD Disable Function Auto-zero capacitor pin. A capacitor between this pin and CAZP cancels any offset inherent to the limiting amplifier. Auto-zero capacitor pin. A capacitor between this pin and CAZN cancels any offset inherent to the limiting amplifier. Analog ground pin. Ground for PECL operation or -3.3V to -5V for standard ECL operation. GNDA and GNDE must be at the same potential. Differential data input. Analog power supply pin. +3.3V to +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the same potential. Filter capacitor for the level detect comparator. Capacitor should be connected to VCCA. When asserted LOW, or left open and pulled LOW via the input pulldown resistor, the output buffer will be enabled and will respond to the input stimulus on the Din input. Forcing Disable HIGH will force the Dout output LOW and its complimentary output HIGH. Loss of signal. This output will go HIGH when the input signal falls below (Vset/100) mVP-P. Digital ground pin. Ground for PECL operation or -3.3V to -5V for standard ECL operation. GNDA and GNDE must be at the same potential. Differential data outputs. Digital power supply pin. +3.3V to +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the same potential. Reference voltage for threshold level set voltage division network. Input threshold level detect setting input. Input generated from voltage divider between Vref and GNDA.
LOS GNDE Dout, Dout VCCE Vref Vset
1 CAZ 2 3 Cin 4 DATA IN Cin 5 5V Cbypass CAZ 7 8 6
CAZN CAZP GNDA Din Din VCCA CLD Disable
Vset 16 Vref 15 VCCE 14 Dout 13 Dout 12 50 GNDE 11 LOS 10 LOS 9 50 50 LEVEL DETECT OUT 50 DATA OUT 3V R1 R2
5V Cbypass
Figure 1. Typical Operating Circuit
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10LVSX1125
Coupling Capacitors The LVSX1125 inputs must be AC coupled to allow proper operation of the offset correction function. The coupling capacitors, Cin, must be large enough to pass the lowest input frequency of interest. Cin where Input Signal Level Detector The LVSX1125 allows for user programmable input signal level-detection and can automatically disable the switching of its ECL data output if the input level is below a set threshold. This prevents the outputs from reacting to noise in the absence of a valid input signal, and ensures that data will only be transmitted when the signal-to-noise ratio is sufficient for low bit-error-rate system operation. Complimentary ECL flags (LOS and LOSB) indicate whether the input signal is above or below the desired threshold level. In the level detect system, the input signal is amplified and rectified before being compared to a programmable reference. A filter is included to prevent noise spikes from triggering the level-detector. The filter has a nominal 1s time constant, and additional filtering can be achieved by using an external capacitor (CLD) from Pin 7 to VCCA (the internal driving impedance is nominally 28k). The formula for the calculation of the CLD capacitor is: CLD where
+ 2p (Rin1) (flow)
Rin = input resistance = 5000 flow = lowest frequency.
Auto-zero Capacitors A feedback amplifier is used to cancel the offset voltage of the forward signal path, so the input to the internal ECL comparator is at its toggle point in the absence of any input signal. The time constant of the cancelling circuitry is set by an external capacitor (CAZ) connected between Pins 1 and 2. The formula for the calculation of the auto-zero capacitor is: CAZ where 150 + 2p (RAZ) (flow) RAZ = internal driving impedance = 290k flow = lowest frequency.
+ RtZ
RZ = internal driving impedance = 28k t = LOS filter time constant.
DC CHARACTERISTICS (GNDA = GNDE = Ground; VCCA = VCCE = 4.5V to 5.5V)
Symbol VIN VOS VN VTH VHYS IIH ICC Characteristic Input Signal Voltage (Din) Input Offset Voltage Input RMS Noise Input Level Detect Programmability Level Detect Hysteresis Input HIGH Current Disable Power Supply Current 33 8.0 1.5 2.5 Single-Ended Min 0.008 Typ Max 1.5 50 225 20 7.0 150 45 Unit VP-P V V mVP-P dB A mA Note 2. Condition Note 1.
1. This device functions with Vinmin = 6mVP-P, but with increased BER (See BER data). 2. This device has an anomoly in VHYS when 0.65 < VSET < 0.75V. Operation in this region is not recommended. (See Figure 3)
35 30 V IN (mVpp) 25 20 15 10 5 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 Input detect level (LOS 1 0) V HYS (dB)
8 7 6 5 4 3 2 1 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
Vset (V)
Vset (V)
Figure 2. LOS versus Vset (TA = 25C)
Figure 3. LOS Hysteresis (TA = 25C)
ECLinPS and ECLinPS Lite DL140 -- Rev 3
3
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MC10LVSX1125
I/O DC CHARACTERISTICS1
-40C Symbol VOH Characteristic Output HIGH Voltage VCC = -4.5 to -5.5V VCC = 5.0V2 Output LOW Voltage VCC = -4.5 to -5.5V VCC = 5.0V2 Input HIGH Voltage3 VCC = -4.5 to -5.5V VCC = 5.0V2 Input LOW Voltage3 VCC = -4.5 to -5.5V VCC = 5.0V2 Input LOW Current3 Min 1080 3920 -1950 3050 -1230 3770 -1950 3050 Max -890 4110 -1650 3350 -890 4110 -1500 3500 Min 1020 3980 -1950 3050 -1170 3830 -1950 3050 0C Max -840 4160 -1630 3370 -840 4160 -1480 3520 Min -980 4020 -1950 3050 -1130 3870 -1950 3050 25C Max -810 4190 -1630 3370 -810 4190 -1480 3520 Min -910 4090 -1950 3050 -1060 3940 -1950 3050 85C Max -720 4280 mV -1595 3405 mV -720 4280 mV -1445 3555 Unit mV
VOL
VIH
VIL
IIL 0.5 0.5 0.5 0.3 A 1. 10SX circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. Outputs are terminated through a 50 resistor to -2.0 volts except where otherwise specified on the individual data sheets. 2. Limits hold for VCC = 5.0V only. Parametric values will vary 1:1 with any variation of VCC. 3. Parametric values for the Disable input only.
AC CHARACTERISTICS (VCCA = VCCE = 4.5V to 5.5V)
Symbol BWmin BWmax tPWD tr, tf RAZ RF tLD tjitter Characteristic Lower -3dB Bandwidth Upper -3dB Bandwidth Pulse Width Distortion Rise/Fall Times Auto-Zero Output Resistance Level Detect Filter Resistance Level Detect Time Constant Total Jitter 100 200 14 0.5 TBD 200 325 25 550 70 300 450 41 4.0 Min Typ Max 20 Unit kHz MHz ps ps k k s ps 20% - 80% Condition
BER (Bit-Error-Rate) Using a 622Mb/s SONET STS-12 pattern, the LVSX1125 shows the following typical BERs at T = 25C:
Input Vpp 6mV 7mV 8mV BER 4E-13 <1E-14 <5E-15
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10LVSX1125
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 -ANOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
-B1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -TSEATING PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
TB
S
A
S
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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MC10LVSX1125
NOTES
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ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC10LVSX1125
NOTES
ECLinPS and ECLinPS Lite DL140 -- Rev 3
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MOTOROLA
MC10LVSX1125
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. - http://sps.motorola.com/mfax/ 852-26668334 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488
MOTOROLA 8
MC10LVSX1125/D ECLinPS and ECLinPS Lite DL140 -- Rev 3

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